This invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a multilayer wiring structure formed by using a so-called damascene process and also to a technology that can effectively be applied to a semiconductor having such a multilayer wiring structure.
In the current trend toward high performance micro-semiconductor devices, the multilayer wiring technology is indispensable for manufacturing such semiconductor devices. There is a well known technique of forming a wiring layer in a semiconductor integrated circuit by forming a thin film of a high melting point metal such as an aluminum (Al) alloy or tungsten (W) on an insulating film, subsequently forming on the thin film a resist pattern having a profile same as the wiring pattern to be produced there from the metal thin film by photolithography and then dry etching the thin film, using the resist pattern as mask. However, the technique of using an Al alloy or some other metal material has a major drawback that the wiring resistance rises remarkably to consequently increase the wiring delay and degrade the performance of the semiconductor device as the wiring is down-sized. Particularly, in the case of high performance logic LSIs, the drawback can severely damage the performance thereof.
As an attempt for bypassing this problem, there has been proposed a process of burying a wiring metal material containing copper (Cu) as principal conductor in the grooves formed on an insulating film and subsequently removing the unnecessary metal outside the grooves by means of a CMP (chemical mechanical polishing) technique to produce a wiring pattern in the grooves (so-called damascene process).
However, as a result of research efforts, the inventors of the present invention came to find that the damascene process, more particularly the dual-damascene process (for producing both the wiring and the interlayer connection wiring of a semiconductor device simultaneously after forming wiring grooves for wiring and contact holes for interlayer connections) is accompanied by a problem as described below that has not hitherto been known.
Firstly, either of two methods may be employed for forming groves (wiring grooves) and holes (connection holes) in the dual-damascene process; a hole-first method and a self-aligning method.
With the hole-first method, deep holes are firstly formed through an interlayer insulating film (which may be an inter-wire insulating film to be used for wiring) that is formed on a lower wiring layer until they get to the latter. To do this, a photoresist film patterned to show so may openings is formed on the interlayer insulating film and then the interlayer insulating film is dry etched by using the photoresist pattern as mask. Subsequently, the holes are filled with an anti-reflection material or resist and then wiring grooves are formed in the interlayer insulating film. To form wiring grooves, a photoresist film having opening for the grooves is formed on the interlayer insulating film and then the interlayer insulating film is dry etched using the photoresist pattern as mask. The holes are filled with the an anti-reflection material before forming the wiring grooves as described above in order to make the photoresist film for forming the wiring grooves to be accurately exposed to light and improve the processing accuracy. In other words, unless the holes are not filled with an anti-reflection material, the surface of the photoresist film reflects the profiles of the holes in the corresponding areas during the exposure operation to come to show undulations and no satisfactory surface flatness can be obtained. When the photoresist film is exposed to light with undulations on the surface, the light irradiating the photoresist pattern is scattered by the undulations (where the holes are formed) to make it no longer possible to accurately form the grooves in the interlayer insulating film. Particularly, because grooves may be formed in the holes (contact holes) for forming wires connecting the upper and lower wiring layers, the problem of poor processing accuracy occurs in many of those holes.
It is true that the problem that arises when the wiring groove pattern is exposed to light can be substantially dissolved by filling the holes with an anti-reflection material. Then the anti-reflection material left in the holes has to be removed after forming the wiring grooves. However, it is highly difficult to satisfactorily remove the filled material and the material remaining in the bottoms of the contact holes can give rise to a problem of insufficient connection or increased connection resistance between the upper and lower wiring layers. Particularly, the problem is ever more serious in recent year as a result of the trend of down-sizing semiconductor devices because the contact holes are also down-sized to give rise to an increased aspect ratio.
With the self-aligning method, on the other hand, wiring grooves and contact holes are formed in a manner as described below. An interlayer insulating film (which is not an inter-wire insulating film) is formed on the lower wiring layer and a silicon nitride film is formed thereon. Then, the silicon nitride film is subjected to a patterning process to produce holes and, thereafter, an inter-wire insulating film (which may typically be a silicon oxide film) is formed further thereon. In other words, an intermediary layer (silicon nitride film layer) processed to show a hole pattern is formed between the interlayer insulating film and the inter-wire insulating film. Then, a groove pattern is formed in the inter-wire insulating film. After the above process of forming the groove pattern, the inter-wire insulating film is subjected to a process of forming holes therethrough by using the intermediary layer (the silicon nitride film having a groove pattern) as mask. The self-aligning method is free from the problem of the residue of the material filled in the holes (contact holes) and that of poor processing accuracy that arises when the grooves are formed.
However, the intermediary layer is formed to operate as etching stopper in the process of forming the grooves (by etching) and also in the process of forming the holes and hence has to have a considerable film thickness. As a result of a study made by the inventors of the present invention, it was found that the intermediary layer is required to be at least about 100 nm thick if it operates properly. Silicon nitride is a highly dielectric material and operates negatively for reducing the dielectric constant of the interlayer insulating film and that of the inter-wire insulating film. A high dielectric constant between wires or between wiring layers gives rise to a large inter-wire capacitance, which by turn obstructs any attempt for realizing a high performance semiconductor device that operates at high speed. Additionally, since the holes are defined in the areas where both wires and holes are formed by dry etching, the holes produced there may have a reduced diameter when the mask for forming the holes and the one for forming the grooves are misaligned. Holes having a reduced diameter can obstruct the effort for providing the inter-wire connection wiring with a required level of resistance and hence again any attempt for realizing a high performance semiconductor device that operates at high speed.
If a large groove pattern is used to avoid the misalignment of the masks, it is no longer possible to reduce both the width of the wires and the distances separating the wiring layers to micro-dimensions. Therefore, the attempt for realizing a high performance semiconductor device will be baffled.
In view of the above identified circumstances, therefore an object of the present invention is to eliminate the residue of foreign objects that can be left in the contact holes of a semiconductor device in order to improve the reliability of the wire connections and the performance of the device even when very fine dual damascene grooves are formed there.
Another object of the present invention is to provide a technique for securing a sufficient area to be used for the process of forming contact holes and reducing the connection resistance between the wiring layers of a semiconductor device in order to improve the performance of the device.
Still another object of the present invention is to provide a technique for reducing the inter-wire capacitance of a semiconductor device in order to improve the performance of the device.
Still another object of the present invention is to provide a technique for improving the degree of integration of a semiconductor device.
The above and other objects of the present invention as well as the novel features of the present invention will become apparent from the described made hereinafter by referring to the accompanying drawings.
Firstly, the present invention will be briefly summarized below.
With a method of manufacturing semiconductor device according to the invention, a wiring groove pattern layer is formed on an insulating layer (including an interlayer insulating film and an inter-wire insulating film) formed on a substrate so as to make it operate as etching mask when forming wiring grooves. Then, a hole pattern layer is formed on the wiring groove pattern layer to make it operate as etching mask when forming interlayer contact holes. Thereafter, the hole pattern is made to transfer into the insulating layer with a predetermined depth by means of a dry etching operation conducted on the hole pattern layer. Then, the hole pattern layer is only removed to operate the insulating layer with use of the hole pattern transferred on the insulating layer and of the wiring groove pattern layer as mask.
Both a semiconductor device and a method of manufacturing a semiconductor device according to the present invention are intended to provide a wiring structure where the width of the wires is not partly enlarged in an attempt for absorbing any possible misalignment of interlayer contact holes. Therefore, according to the invention, it is now possible to reduce the inter-wire intervals to the minimal limit defined by photolithography. Then, there may arise a problem of misalignment between the wiring groove pattern layer and the hole pattern formed thereon. According to the invention, this misalignment problem can be dissolved either of the two techniques as discussed below. Firstly, it can be dissolved by dry etching the wiring groove pattern layer from above through the hole pattern layer before transferring the hole pattern into the insulating layer with a predetermined depth. Secondly it can be dissolved by using a hole pattern having a hole diameter greater than the width of the wiring grooves as measured transversally relative to the longitudinal direction of the grooves of the groove pattern and dry etching the hole pattern layer from above under the condition that the wiring groove pattern layer is not etched when transferring the hole pattern into the insulating layer with a predetermined depth.
With a method of manufacturing a semiconductor device according to the invention, a thin silicon nitride film having a film thickness of about 50 nm is used for the wiring groove pattern layer formed on the insulating film. Since the wiring groove pattern layer is sufficiently thin, the hole pattern layer formed thereon can be processed with a satisfactory degree of accuracy. More specifically, according to the invention, a resist pattern (which is the pattern layer for forming the hole pattern layer) is formed on a small step as low as about 50 nm and hence the step can be made harmless simply by applying an anti-reflection film before applying resist. Therefore, unlike the above described hole-first method, no flattening operation (of filling the contact holes with an anti-reflection material) is required. Additionally, as for the possible misalignment of the wiring groove pattern and the hole pattern, the hole pattern can be formed through the wiring groove pattern layer in the initial stages of the etching operation for transferring the hole pattern into the insulating layer with a predetermined depth. It will be appreciated that, since a very thin silicon nitride film is used for the wiring groove pattern layer, the etching operation can be carried out without any difficulty. In other words, the disadvantages of the self-aligning method can be eliminated by forming the holes firstly and securing a desired hole diameter. While a problem of insufficient etching may arise at the bottoms of the holes formed through the insulating layer and showing misalignment to a slight extent, it can be avoided by arranging an etching stopper layer under the insulating layer to accommodate a possible excessively etched condition of the holes. When, on the other hand, using a hole pattern having a hole diameter greater than the width of the wiring grooves as measured transversally relative to the longitudinal direction of the grooves of the groove pattern and dry etching the hole pattern layer from above under the condition that the wiring groove pattern layer is not etched for transferring the hole pattern into the insulating layer with a predetermined depth, the hole pattern is transferred by etching in the areas where the wiring groove pattern and the hole pattern having holes with a diameter greater than the width of the wiring grooves are overlapping. Then, as the hole pattern layer has holes with a diameter greater than the width of the wiring grooves to accommodate any possible misalignment of the masks, the holes will be made to show a diameter same as the width of the grooves.
With this arrangement, the disadvantages of the hole-first method including the problem of the residue of the material filled in the contact holes can be eliminated while maintaining the advantages of the method including the easiness of securing the contact hole diameter. In other words, according to the invention, the hole pattern is dry etched before dry etching the groove pattern so that the holes are defined firstly particularly in terms of diameter and hence the diameter of the holes would not be reduced due to any misalignment.
As for the silicon nitride film that operates as stopper layer, it is used as etching stopper for the groove pattern and also as dry etching mask for the hole pattern with the known self-aligning method so that it needs to have a film thickness at least as large as 100 nm. With a method according to the invention, on the other hand, the silicon nitride film is required to operate only as etching stopper for the groove pattern so that it is possible to reduce the intermediary layer if compared with its counterpart used with the known self-aligning method. Additionally, the use of the intermediary can be avoided by controlling the duration of the etching operation and hence the depth of the hole pattern. As a result, the inter-wire capacitance of the semiconductor device can be reduced to improve the performance of the device.
Various aspect of the present invention will be listed below.
1. A method of manufacturing a semiconductor device comprising:
(a) a step of forming a first insulating layer on a substrate;
(b) a step of forming a wiring groove pattern layer on the first insulating layer to operate as etching mask when forming wiring grooves;
(c) a step of forming a hole pattern layer on the wiring groove pattern layer to operate as etching mask when forming contact holes;
(d) a step of etching the wiring groove pattern layer and the first insulating layer in the presence of the hole pattern layer and transferring the hole pattern having a predetermined depth into the first insulating layer;
(e) a step of removing the hole pattern layer; and
(f) a step of etching the first insulating layer in the presence of the wiring groove pattern layer and the hole pattern and transferring the wiring groove pattern into the first insulating layer.
2. A method of manufacturing a semiconductor device comprising wiring grooves formed with a predetermined width, wires formed in the wiring grooves and interlayer connecting members connecting the wires and lower wires thereof arranged therebelow; said method comprising steps of:
(a) a step of forming a first insulating layer on a substrate;
(b) a step of forming a wiring groove pattern layer on the first insulating layer to operate as etching mask when forming wiring grooves;
(c) a step of forming a hole pattern layer on the wiring groove pattern layer to operate as etching mask when forming contact holes for accommodating interlayer connecting members therein;
(d) a step of etching the wiring groove pattern layer and the first insulating layer in the presence of the hole pattern layer and transferring the hole pattern having a predetermined depth into the first insulating layer;
(e) a step of removing the hole pattern layer; and
(f) a step of etching the first insulating layer in the presence of the wiring groove pattern layer and the hole pattern.
3. A method of manufacturing a semiconductor device comprising wiring grooves formed with a predetermined width, wires formed in the wiring grooves and interlayer connecting members connecting the wires and lower wires thereof arranged therebelow; said method comprising steps of:
(a) a step of forming a first insulating layer on a substrate;
(b) a step of forming a wiring groove pattern layer on the first insulating layer to operate as etching mask when forming wiring grooves;
(c) a step of forming a hole pattern layer on the wiring groove pattern layer to make the former operate as etching mask when forming contact holes for accommodating interlayer connecting members therein with a hole diameter of the hole pattern layer substantially same as the groove width of the wiring groove pattern layer;
(d) a step of etching the wiring groove pattern layer and the first insulating layer in the presence of the hole pattern layer and transferring the hole pattern having a predetermined depth into the first insulating layer;
(e) a step of removing the hole pattern layer; and
(f) a step of etching the first insulating layer in the presence of the wiring groove pattern layer and the hole pattern.
A method of manufacturing a semiconductor device as set forth in 2 or 3 above, wherein the wiring groove pattern layer is partly etched with the first insulating layer in the etching step of (d).
5. A method of manufacturing a semiconductor device as set forth in any 1 through 4 above, wherein
the hole pattern is formed to a lower portion of the first insulating layer in step (d) and the wiring grooves are formed in step (f).
6. A method of manufacturing a semiconductor device as set forth in any of 1 through 4 above, wherein
the hole pattern is formed halfway through the first insulating layer in step (d) and the wiring grooves and the contact holes are formed in step (f).
7. A method of manufacturing a semiconductor device as set forth in any of 1 through 6 above, further comprising;
a step of forming a second insulating layer showing an etching selectivity relative to the first insulating layer prior to step (a);
the dry etching of step (f) being conducted in two sub-steps including a first sub-step of etching the first insulating layer at a rate lower than a rate of etching the second insulating layer and a second sub-step of etching the first insulating layer at a rate same as a rate of etching the second insulating layer.
8. A method of manufacturing a semiconductor device comprising:
(a) a step of sequentially forming a first stopper/insulating layer, a first insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern layer for contact holes after step (b);
(d) a step of etching the first insulating layer halfway under condition of removing the stopper layer and the first insulating layer in the presence of the hole pattern layer and transferring the hole pattern;
(e) a step of removing the hole pattern layer; and
(f) a step of etching the first insulating layer in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein and forming the contact holes and the wiring grooves.
9. A method of manufacturing a semiconductor device as set forth in any of 1 through 8 above, wherein
the hole pattern layer is formed with openings of stacked vias in step (c) and the hole pattern is formed to a lower portion of the first insulating layer in step (d).
10. A method of manufacturing a semiconductor device as set forth in any of 1 through 9 above, further comprising:
a step of forming a flattening film between step (b) and step (c).
11. A method of manufacturing a semiconductor device as set forth in 10 above wherein
the flattening film is an anti-reflection film
12. A method of manufacturing a semiconductor device as set forth in any of 1 through 11 above, wherein
the wiring grooves and the contact holes are formed in step (f) and subsequently a conductive film is buried in the wiring grooves and the contact holes to form wires and interlayer connecting members.
13. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and lower wires thereof arranged therebelow; said method comprising:
(a) a step of sequentially forming a first stopper/insulating layer, an interlayer insulating layer, a second stopper/insulating layer, an inter-wire insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein after step (b);
(d) a step of etching the inter-wire insulating layer and the second stopper/insulating layer in the presence of the hole pattern mask and transferring the hole pattern into the first insulating layer;
(e) a step of removing the hole pattern layer; and
(f) a step of conducting an etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein.
14. A method of manufacturing a semiconductor device as set forth in 13 above, wherein
the resist layer used for forming the wiring groove pattern is removed after transferring the wiring groove pattern in step (b) and a hole pattern mask is formed directly on the stopper layer.
15. A method of manufacturing a semiconductor device as set forth in 13 or 14 above, wherein
the etching operation of step (f) is completed or terminated in the first stopper/insulating layer in the hole pattern region and in the second stopper/insulating layer in the wiring groove pattern region.
16. A method of manufacturing a semiconductor device as set forth in 13, 14 or 15 above, wherein
the first and second stopper/insulating layers and the stopper layer are made of silicon nitride film.
17. A method of manufacturing a semiconductor device as set forth in 16 above, wherein
the stopper layer has a film thickness greater than the first and second stopper/insulating layers.
18. A method of manufacturing a semiconductor device as set forth in any of 13 through 17 above, wherein
the hole pattern mask is a resist mask.
19. A method of manufacturing a semiconductor device as set forth in any of 13 through 18 above, further comprising:
a step of removing the stopper layer after the step of (f).
20. A method of manufacturing a semiconductor device as set forth in 15 above, further comprising:
a step of removing the stopper layer and the first and second stopper layers after the step of (f);
subsequently a conductive film being buried in the wiring grooves and the contact holes to form wires and interlayer connecting members.
21. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of sequentially forming a first stopper/insulating layer, a first insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) a step of etching the stopper layer and the first insulating layer in the presence of the hole pattern mask and transferring the hole pattern halfway into the first insulating layer;
(e) a step of removing the hole pattern layer; and
(f) a step of conducting an etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves.
22. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of sequentially forming a first stopper/insulating layer, a first interlayer insulating layer, a marker insulating layer, a second interlayer insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) etching the second interlayer insulating layer and the marker insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) removing the hole pattern layer; and
(f) conducting an etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves;
the completion of the etching process of step (d) being detected by detecting plasma light emission of the elements contained in the marker insulating layer;
completion of the etching process on the hole pattern in step (f) being detected by the time of getting to the first stopper/insulating layer.
23. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and lower wires thereof arranged therebelow; said method comprising:
(a) a step of sequentially forming a first interlayer insulating layer, a marker insulating layer, a second interlayer insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) etching the second interlayer insulating layer and the marker insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) removing the hole pattern layer; and
(f) conducting an etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves;
completion of the etching process of step (f) being detected by detecting plasma light emission of the elements contained in the marker insulating layer.
24. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of sequentially forming a first stopper/insulating layer, a first interlayer insulating layer, a second stopper/insulating layer, a second interlayer insulating layer, a marker insulating layer, a third interlayer insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) etching the third interlayer insulating layer, the marker insulating layer, the second interlayer insulating layer and the second stopper/insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) removing the hole pattern layer; and
(f) conducting an etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves simultaneously;
completion of step (f) of etching the groove pattern being detected by detecting plasma light emission of the elements contained in the marker insulating layer.
25. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of sequentially forming a first interlayer insulating layer, a second interlayer insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) etching the stopper layer and the second interlayer insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) removing the hole pattern layer; and
(f) conducting an etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves simultaneously;
the first interlayer insulating layer and the second interlayer insulating layer being made of respective materials showing different etching rates;
completion of the etching process on the wiring groove pattern in step (f) being detected by the time of getting to the second interlayer insulating layer.
26. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of forming a first insulating layer;
(b) a step of forming a wiring groove pattern layer on the first insulating layer to operate as etching mask when forming wiring grooves;
(c) a step of forming a hole pattern layer on. the wiring groove pattern layer to make the former operate as etching mask when forming contact holes for accommodating interlayer connecting members to be formed therein;
(d) a step of conducting an etching operation in the presence of the hole pattern layer with a rate of etching the wiring groove pattern layer lower than the rate of etching the first insulating layer;
(e) a step of removing the hole pattern layer; and
(f) a step of conducting an etching operation in the presence of the wiring groove pattern and the hole pattern.
27. A method of manufacturing a semiconductor device as set forth in 26 above, wherein
the hole diameter of the hole pattern as measured in the direction transversal to the wiring groove pattern layer is greater than the groove width of the wiring groove pattern layer.
28. A method of manufacturing a semiconductor device as set forth in any of 1 through 27 above, further comprising;
(g) a step of forming a barrier metal layer and a copper layer on an entire surface of the substrate; and
(h) a step of removing the barrier metal layer and the copper layer by chemical mechanical polishing except an inside of the wiring grooves and the contact holes formed by the etching process of step (f).
29. A method of manufacturing a semiconductor device as set forth in 28 above, wherein
the wiring groove pattern layer or the stopper layer is removed in the step of (h).
30. A method of manufacturing a semiconductor device as set forth in 29 above, wherein
a mask layer for patterning the wiring groove pattern layer or the stopper layer is formed by using a conductive material.
31. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of sequentially forming a first insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) a step of conducting a first etching operation of partly etching the stopper layer and the first insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) a step of removing the hole pattern layer; and
(f) a step of conducting a second etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves;
the stopper layer and the ridges of the first insulating layer being etched in either or both of the first and second etching operations.
32. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of sequentially forming a first insulating layer and a stopper layer;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) a step of conducting a first etching operation of etching part of the first insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) a step of removing the hole pattern layer; and
(f) a step of conducting a second etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves;
ends of the stopper layer being etched at least in either of the first and second etching operations.
33. A method of manufacturing a semiconductor device as set forth in 31 or 32 above, further comprising:
(g) a step of forming a barrier metal layer and a copper layer on an entire surface of the substrate; and
(h) a step of removing the barrier metal layer and the copper layer by chemical mechanical polishing except an inside of the wiring grooves and the contact holes formed by the etching process of step (f);
parts of the copper layer and those of the barrier metal layer located on the wiring grooves, the stopper layer and a surface section of the first insulating layer being removed in the step of (h).
34. A method of manufacturing a semiconductor device as set forth in 33 above, wherein
the copper layer includes a first copper layer operating as seed layer and a second copper layer formed by plating.
35. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and lower wires thereof arranged therebelow; said method comprising:
(a) a step of sequentially forming a first insulating layer and a stopper layer on the lower wires;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) a step of etching the first insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) a step of removing the hole pattern layer; and
(f) a step of conducting a second etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves;
the hole pattern mask of the step of (c) being formed in alignment with the lower wires.
36. A method of manufacturing a semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and the lower wires arranged therebelow; said method comprising:
(a) a step of sequentially forming a first insulating layer and a stopper layer on the lower wires;
(b) a step of transferring a wiring groove pattern into the stopper layer;
(c) a step of forming a hole pattern mask for contact holes for accommodating interlayer connecting members to be formed therein;
(d) a step of etching the first insulating layer in the presence of the hole pattern mask and transferring the hole pattern;
(e) a step of removing the hole pattern layer; and
(f) a step of conducting a second etching operation in the presence of the stopper layer having the hole pattern and the wiring groove pattern formed therein to form contact holes and wiring grooves;
the hole pattern mask of the step of (c) being formed in alignment with center of the lower wires and that of the wiring groove pattern.
37. A method of manufacturing a semiconductor device as set forth in any of 1 through 36 above, wherein
the plan of the contact holes is formed by transferring the plan of the hole pattern of step (c); and
the plan of the wires is formed by transferring the plan of the pattern of step (b) ant that of step (c).
38. A method of manufacturing a semiconductor device as set forth in any of 1 through 37 above, wherein
the mask of step (b) is formed by using resist or a hard mask.
39. A method of manufacturing a semiconductor device as set forth in any of 1 through 38 above, wherein
the diameter of the contact holes and the width of the wires shows a substantially same value.
40. A semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and lower wires thereof arranged therebelow;
an interlayer insulating layer containing a marker insulating layer being formed to separate the lower wires and the wires in the wiring grooves;
the marker insulating layer being formed between bottoms of the wiring grooves and the lower wires.
41. A semiconductor device comprising wires formed in wiring grooves and interlayer connecting members connecting the wires and lower wires thereof arranged therebelow;
the wires having a cross section with its width increasing toward a surface so as to increase an angle of inclination.
42. A method of manufacturing a semiconductor device comprising:
a step of forming an anti-reflection film on an insulating film having a flattened surface and provided with wires arranged thereunder; and
a step of applying resist onto the anti-reflection film to form a resist film and irradiating the resist film with patterned light for exposure.
43. A method of manufacturing a semiconductor device as set forth in 42 above, wherein
the wires are formed by burying conductive members in wiring grooves formed in a lower insulating film layer of the insulating film and removing the conductive members by means of a CMP method from the areas other than the wiring grooves and the insulating film is formed with the flattened surface on the lower wires and the wires by means of a deposition method.
44. A method of manufacturing a semiconductor device as set forth in 42 above, wherein
the wires are formed by depositing a conductive film and patterning the film by means of a photolithography method and the insulating film is formed with the flattened surface by depositing an insulating film to cover the wires and polishing the surface of the deposited insulating by means of a CMP method.
45. A method of manufacturing a semiconductor device comprising:
a step of depositing a second insulating film on a first insulating film, the second insulating film showing an etching selectivity relative to the first insulating layer;
a step of forming a first resist film patterned to show a wiring groove pattern on the second insulating film;
a step of etching the second insulating film in the presence of the first resist film and transferring the wiring groove pattern into the second insulating film;
a step of forming an anti-reflection film on the second insulating film;
a step of applying resist onto the anti-reflection film to form a second resist film; and
a step of irradiating the second resist film with light showing a contact hole pattern for exposure.
46. A method of manufacturing a semiconductor device as set forth in 45 above, wherein
the second insulating film has a film thickness small enough for the surface thereof to be regarded as flat after forming the anti-reflection film.
47. A method of manufacturing a semiconductor device as set forth in 45 or 46 above, wherein
the second insulating film has a film thickness smaller than the first insulating and the second resist film.
48. A method of manufacturing a semiconductor device comprising:
a step of forming a mask for wiring grooves and subsequently forming an anti-reflection film;
a step of forming a mask for contact holes on the anti-reflection film; and
a step of transferring wiring grooves and contact holes into the insulating film by using the mask for wiring grooves and the mask for contact holes.
49. A method of manufacturing a semiconductor device as set forth in 48 above, wherein
the anti-reflection film operates as flattening film.
50. A method of manufacturing a semiconductor device comprising:
a step of forming a mask for wiring grooves and subsequently forming a flattening film;
a step of forming a mask for contact holes on the flattening film; and
a step of transferring wiring grooves and contact holes into the insulating film by using the mask for wiring grooves and the mask for contact holes.
51. A method of manufacturing a semiconductor device as set forth in 50 above, wherein
the flattening film and the mask for wiring grooves are removed in a self-aligning manner relative to the mask for contact holes.
52. A semiconductor device comprising:
wiring grooves formed in an interlayer insulating film;
wires formed in the wiring grooves;
contact holes formed in the interlayer insulating film; and
connecting members formed in the contact holes;
diameter of the contact holes and width of the wires showing a substantially same value;
the wires and the connecting members being formed integrally.
53. A semiconductor device as set forth in 52 above, wherein
the plan of the wires is formed from the plan of the contact holes and the diameter of the contact holes as measured in the direction transversal to the wiring grooves.
54. A semiconductor device as set forth in 52 above, wherein
the wiring grooves and the contact holes overlap with each other in terms of the area of the plan of the contact holes.
55. A semiconductor device as set forth in 52, 53 or 54 above, further comprising:
first wires having a predetermined width greater than the diameter of the contact holes;
the first wires and the contact holes overlap with each other in terms of the area of the plan of the contact holes.
56. A method of manufacturing a semiconductor device comprising:
a step of forming a first mask film on a film to be patterned and subsequently forming an anti-reflection film;
a step of forming a second mask film on the anti-reflection film; and
a step of transferring a pattern into the film to be patterned by using the first and second mask films.
57. A method of manufacturing a semiconductor device comprising:
a step of forming a first mask film on a film to be patterned and subsequently forming a flattening film;
a step of forming a second mask film on the flattening film; and
a step of transferring a pattern into the film to be patterned by using the first and second mask films.
58. A method of manufacturing a semiconductor device as set forth in 56 or 57 above, wherein
the anti-reflection film or the flattening film and the first mask film are removed in a self-aligning manner relative to the second mask film.